Recent questions tagged analog-and-digital-electronics / GO Electrical

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GATE Electrical 2021 | Question: 37
A counter is constructed with three $D$ flip-flops. The input-output pairs are named $(D_{0},\:Q_{0})$, $(D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$, where the subscript $0$ denotes the least significant bit. The output sequence is desired to be the Gray- ... $\overline{Q_{2}}Q_{0}+Q_{1}\overline{Q_{0}}$ $Q_{2}Q_{1}+\overline{Q_{2}}\:\overline{Q_{1}}$

A counter is constructed with three $D$ flip-flops. The input-output pairs are named $(D_{0},\:Q_{0})$, $(D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$, wher...

Arjun

15.9k points

Arjun asked Feb 19, 2021

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GATE Electrical 2019 | Question: 35
The output expression for the Karnaugh map shown below is $Q \bar{R} +S$ $Q \bar{R} + \bar{S}$ $QR+S$ $Q R +\bar{S}$

The output expression for the Karnaugh map shown below is$Q \bar{R} +S$$Q \bar{R} + \bar{S}$$QR+S$$Q R +\bar{S}$

Arjun

15.9k points

Arjun asked Feb 12, 2019

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GATE Electrical 2019 | Question: 36
In the circuit shown below, $X$ and $Y$ are digital inputs, and $Z$ is a digital output. The Equivalent circuit is a NAND gate NOR gate XOR gate XNOR gate

In the circuit shown below, $X$ and $Y$ are digital inputs, and $Z$ is a digital output. The Equivalent circuit is aNAND gateNOR gateXOR gateXNOR gate

Arjun

15.9k points

Arjun asked Feb 12, 2019

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4

GATE Electrical 2012 | Question: 7
In the sum of products function $f(X,Y,Z) = \Sigma(2,3,4,5)$, the prime implicants are $\overline{X}Y, X \overline{Y}$ $\overline{X}Y, X \overline{Y}\overline{Z}, X \overline{Y}Z$ $\overline{X} Y \overline{Z}, \overline{X}YZ, X \overline{Y}$ $\overline{X} Y \overline{Z}, \overline{X}YZ, X \overline{Y} \overline{Z}, X \overline{Y}Z$

In the sum of products function $f(X,Y,Z) = \Sigma(2,3,4,5)$, the prime implicants are$\overline{X}Y, X \overline{Y}$$\overline{X}Y, X \overline{Y}\overline{Z}, X \overli...

Andrijana3306

1.4k points

Andrijana3306 asked Mar 23, 2018

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GATE Electrical 2018 | Question: 37
Digital input signals A, B, C with A as the MSB and C as the LSB are used to realize the Boolean function $F=m_0+m_2+m_3+m_5+m_7$, where $m_i$ denotes the $i$ th minterm. In addition, $F$ has a don't care for $m_1$. The simplified expression for $F$ is given by ... $\overline{A}+C$ $\overline{C}+A$ $\overline{A} C + BC + A \overline{C}$

Digital input signals A, B, C with A as the MSB and C as the LSB are used to realize the Boolean function $F=m_0+m_2+m_3+m_5+m_7$, where $m_i$ denotes the $i$ th minterm...

Arjun

15.9k points

Arjun asked Feb 19, 2018

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GATE Electrical 2018 | Question: 36
Which one of the following statements is true about the digital circuit shown in the figure It can be used for dividing input frequency by $3$ It can be used for dividing input frequency by $5$ It can be used for dividing input frequency by $7$ It cannot be reliably used as a frequency divider due to disjoint internal cycles

Which one of the following statements is true about the digital circuit shown in the figureIt can be used for dividing input frequency by $3$It can be used for dividing i...

Arjun

15.9k points

Arjun asked Feb 19, 2018

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1 answer

7

GATE Electrical 2018 | Question: 14
In the logic circuit shown in the figure, $Y$ is given by $Y=ABCD$ $Y=(A+B)(C+D)$ $Y=A+B+C+D$ $Y=AB+CD$

In the logic circuit shown in the figure, $Y$ is given by$Y=ABCD$$Y=(A+B)(C+D)$$Y=A+B+C+D$$Y=AB+CD$

Arjun

15.9k points

Arjun asked Feb 19, 2018

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GATE Electrical 2017 Set 2 | Question: 49
For the synchronous sequential circuit shown below, the output $Z$ is zero for the initial conditions $Q_{A}, Q_{B}, Q_{C}= Q'_{A}, Q'_{B}, Q'_{C}=100$ The minimum number of clock cycles after which the output $Z$ would again become zero is _________.

For the synchronous sequential circuit shown below, the output $Z$ is zero for the initial conditions $Q_{A}, Q_{B}, Q_{C}= Q'_{A}, Q'_{B}, Q'_{C}=100$The minimum number ...

Arjun

15.9k points

Arjun asked Feb 26, 2017

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9

GATE Electrical 2017 Set 2 | Question: 10
For a $3$-input logic circuit shown below, the output $Z$ can be expressed as $Q+\overline{R}$ $P\overline{Q}+R$ $\overline{Q}+R$ $P+\overline{Q}+R$

For a $3$-input logic circuit shown below, the output $Z$ can be expressed as $Q+\overline{R}$$P\overline{Q}+R$$\overline{Q}+R$$P+\overline{Q}+R$

Arjun

15.9k points

Arjun asked Feb 26, 2017

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10

GATE Electrical 2017 Set 1 | Question: 36
The output expression for the Karnaugh map shown below is $B \overline{D}+BCD$ $B \overline{D}+AB$ $\overline{B}D+ABC$ $B \overline{D}+ABC$

The output expression for the Karnaugh map shown below is$B \overline{D}+BCD$$B \overline{D}+AB$$\overline{B}D+ABC$$B \overline{D}+ABC$

Arjun

15.9k points

Arjun asked Feb 26, 2017

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11

GATE Electrical 2017 Set 1 | Question: 13
The Boolean expression $AB+A\bar{C}+BC$ simplifies to $BC + A\bar{C}$ $AB + A\bar{C} + B$ $AB + A\bar{C}$ $AB + BC$

The Boolean expression $AB+A\bar{C}+BC$ simplifies to$BC + A\bar{C}$$AB + A\bar{C} + B$$AB + A\bar{C}$$AB + BC$

Arjun

15.9k points

Arjun asked Feb 26, 2017

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12

GATE Electrical 2013 | Question: 37
The clock frequency applied to the digital circuit shown in the figure below is $1$ $kHz$. If the initial state of the output $Q$ of the flip-flop is ‘$0$’, then the frequency of the output waveform $Q$ in $kHz$ is $0.25$ $0.5$ $1$ $2$

The clock frequency applied to the digital circuit shown in the figure below is $1$ $kHz$. If the initial state of the output $Q$ of the flip-flop is ‘$0$’, then the ...

piyag476

1.6k points

piyag476 asked Feb 11, 2017

2 votes

1 answer

13

GATE Electrical 2014 Set 3 | Question: 21
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $X$ is the don’t care condition, and $Q$ is the output representing the state. The logic gate represented by the state diagram is $XOR$ $OR$ $AND$ $NAND$

A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $X$ is the don’t care condition, and $Q$ is the output representing t...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

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14

GATE Electrical 2014 Set 2 | Question: 23
The sinusoidal ac source in the figure has an rms value of $\dfrac{20}{\sqrt{2}}V$ . Considering all possible values of $R_L$, the minimum value of $R_S$ in $\Omega$ to avoid burnout of the Zener diode is _________.

The sinusoidal ac source in the figure has an rms value of $\dfrac{20}{\sqrt{2}}V$ . Considering all possible values of $R_L$, the minimum value of $R_S$ in $\Omega$ to a...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

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15

GATE Electrical 2014 Set 1 | Question: 21
A cascade of three identical modulo - $5$ counters has an overall modulus of $5$ $25$ $125$ $625$

A cascade of three identical modulo - $5$ counters has an overall modulus of$5$$25$$125$$625$

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

1 votes

1 answer

16

GATE Electrical 2015 Set 2 | Question: 38
A Boolean function $f(A, B, C, D) = \prod (1,5,12,15)$ is to be implemented using an $8 \times 1$ multiplexer ($A$ is $MSB$). The inputs $ABC$ are connected to the select inputs $S_{2} S_{1} S_{0}$ of the multiplexer respectively. Which one of the following ... $D, 1, D, 1, 1, 1, \overline{D}, D$ $\overline{D}, 0, \overline{D}, 0, 0, 0,D, \overline{D}$

A Boolean function $f(A, B, C, D) = \prod (1,5,12,15)$ is to be implemented using an $8 \times 1$ multiplexer ($A$ is $MSB$). The inputs $ABC$ are connected to the selec...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

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17

GATE Electrical 2015 Set 2 | Question: 37
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $Q_{1}Q_{0}=00$. The state $(Q_{1}Q_{0})$, immediately after the $333^{rd}$ clock pulse is $00$ $01$ $10$ $11$

In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $Q_{1}Q_{0}=00$. The state $(Q_{1}Q_{0})$, immediately after the $...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

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18

GATE Electrical 2016 Set 2 | Question: 26
The Boolean expression $\overline{(a+\bar{b}+c+\bar{d})+(b+\bar{c})}$ simplifies to $1$ $\overline{a.b}$ $a.b$ $0$

The Boolean expression $\overline{(a+\bar{b}+c+\bar{d})+(b+\bar{c})}$ simplifies to$1$$\overline{a.b}$$a.b$$0$

makhdoom ghaya

9.4k points

makhdoom ghaya asked Jan 29, 2017

0 votes

0 answers

19

GATE Electrical 2016 Set 2 | Question: 1
The output expression for the Karnaugh map shown below is $A+\bar{B}$ $A+\bar{C}$ $\bar{A}+\bar{C}$ $\bar{A}+C$

The output expression for the Karnaugh map shown below is$A+\bar{B}$$A+\bar{C}$$\bar{A}+\bar{C}$$\bar{A}+C$

makhdoom ghaya

9.4k points

makhdoom ghaya asked Jan 29, 2017

2 votes

0 answers

20

GATE Electrical 2016 Set 1 | Question: 11
Consider the following circuit which uses a $2$-to-$1$ multiplexer as shown in the figure below. The Boolean expression for output $F$ in terms of $A$ and $B$ is $A\oplus B$ $\overline{A+B}$ $A+B$ $\overline{A \oplus B}$

Consider the following circuit which uses a $2$-to-$1$ multiplexer as shown in the figure below. The Boolean expression for output $F$ in terms of $A$ and $B$ is$A\oplus ...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Jan 29, 2017