Recent questions tagged sequential-circuit / GO Electrical

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GATE Electrical 2021 | Question: 37
A counter is constructed with three $D$ flip-flops. The input-output pairs are named $(D_{0},\:Q_{0})$, $(D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$, where the subscript $0$ denotes the least significant bit. The output sequence is desired to be the Gray- ... $\overline{Q_{2}}Q_{0}+Q_{1}\overline{Q_{0}}$ $Q_{2}Q_{1}+\overline{Q_{2}}\:\overline{Q_{1}}$

A counter is constructed with three $D$ flip-flops. The input-output pairs are named $(D_{0},\:Q_{0})$, $(D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$, wher...

Arjun

15.9k points

Arjun asked Feb 19, 2021

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GATE Electrical 2018 | Question: 36
Which one of the following statements is true about the digital circuit shown in the figure It can be used for dividing input frequency by $3$ It can be used for dividing input frequency by $5$ It can be used for dividing input frequency by $7$ It cannot be reliably used as a frequency divider due to disjoint internal cycles

Which one of the following statements is true about the digital circuit shown in the figureIt can be used for dividing input frequency by $3$It can be used for dividing i...

Arjun

15.9k points

Arjun asked Feb 19, 2018

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GATE Electrical 2017 Set 2 | Question: 49
For the synchronous sequential circuit shown below, the output $Z$ is zero for the initial conditions $Q_{A}, Q_{B}, Q_{C}= Q'_{A}, Q'_{B}, Q'_{C}=100$ The minimum number of clock cycles after which the output $Z$ would again become zero is _________.

For the synchronous sequential circuit shown below, the output $Z$ is zero for the initial conditions $Q_{A}, Q_{B}, Q_{C}= Q'_{A}, Q'_{B}, Q'_{C}=100$The minimum number ...

Arjun

15.9k points

Arjun asked Feb 26, 2017

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GATE Electrical 2013 | Question: 37
The clock frequency applied to the digital circuit shown in the figure below is $1$ $kHz$. If the initial state of the output $Q$ of the flip-flop is ‘$0$’, then the frequency of the output waveform $Q$ in $kHz$ is $0.25$ $0.5$ $1$ $2$

The clock frequency applied to the digital circuit shown in the figure below is $1$ $kHz$. If the initial state of the output $Q$ of the flip-flop is ‘$0$’, then the ...

piyag476

1.5k points

piyag476 asked Feb 11, 2017

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GATE Electrical 2014 Set 1 | Question: 21
A cascade of three identical modulo - $5$ counters has an overall modulus of $5$ $25$ $125$ $625$

A cascade of three identical modulo - $5$ counters has an overall modulus of$5$$25$$125$$625$

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

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GATE Electrical 2015 Set 2 | Question: 37
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $Q_{1}Q_{0}=00$. The state $(Q_{1}Q_{0})$, immediately after the $333^{rd}$ clock pulse is $00$ $01$ $10$ $11$

In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $Q_{1}Q_{0}=00$. The state $(Q_{1}Q_{0})$, immediately after the $...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017