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GATE Electrical 2014 Set 3 | Question: 52
A hysteresis type $TTL$ inverter is used to realize an oscillator in the circuit shown in the figure. If the lower and upper trigger level voltages are $0.9$ $V$ and $1.7$ $V$, the period (in $ms$), for which output is $LOW$, is __________.

A hysteresis type $TTL$ inverter is used to realize an oscillator in the circuit shown in the figure.If the lower and upper trigger level voltages are $0.9$ $V$ and $1.7$...

makhdoom ghaya

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makhdoom ghaya asked Feb 11, 2017

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GATE Electrical 2014 Set 1 | Question: 22
In the Wien Bridge oscillator circuit shown in figure, the bridge is balanced when $\dfrac{R_3}{R_4}=\dfrac{R_1}{R_2}\, \: \: \omega =\dfrac{1}{\sqrt{R_1C_1R_2C_2}} \\$ ... $\dfrac{R_3}{R_4}+\dfrac{R_1}{R_2}=\dfrac{C_2}{C_1}, \: \: \omega =\dfrac{1}{R_1C_1R_2C_2}$

In the Wien Bridge oscillator circuit shown in figure, the bridge is balanced when$\dfrac{R_3}{R_4}=\dfrac{R_1}{R_2}\, \: \: \omega =\dfrac{1}{\sqrt{R_1C_1R_2C_2}} \\$ $\...

makhdoom ghaya

9.4k points

makhdoom ghaya asked Feb 11, 2017

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