GO Electrical
+2 votes

A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $X$ is the don’t care condition, and $Q$ is the output representing the state.

The logic gate represented by the state diagram is

  1. $XOR$
  2. $OR$
  3. $AND$
  4. $NAND$
in Signals and Systems by (9.3k points)
recategorized by

1 Answer

0 votes
Ans is D )

Becoz Nand output will be zero only when input is 11.

Also for input
0 1

0 0

output is 1 and it can be written as 0X ( x is don't care).

THIS shows that this is Nand Not XOR becoz In XOR for 0,0 output will be 0 .

It can also be derived using truth table .
by (140 points)
Answer:
Welcome to GATE Overflow, Electrical, where you can ask questions and receive answers from other members of the community.

912 questions
38 answers
10 comments
27,188 users