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41
GATE Electrical 2014 Set 1 | Question: 49
Given that the op-amps in the figure are ideal, the output voltage $V_0$ is $(V_1-V_2)$ $2(V_1-V_2)$ $(V_1-V_2)/2$ $(V_1+V_2)$
Given that the op-amps in the figure are ideal, the output voltage $V_0$ is$(V_1-V_2)$$2(V_1-V_2)$$(V_1-V_2)/2$$(V_1+V_2)$
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50
GATE Electrical 2015 Set 2 | Question: 8
In the following circuit, the input voltage $V_{in}$ is $100 \sin(100 \pi t)$. For $100 \pi RC = 50$, the average voltage across $R$ (in Volts) under steady-state is nearest to $100$ $31.8$ $200$ $63.6$
In the following circuit, the input voltage $V_{in}$ is $100 \sin(100 \pi t)$. For $100 \pi RC = 50$, the average voltage across $R$ (in Volts) under steady-state is near...
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51
GATE Electrical 2015 Set 2 | Question: 12
In the following circuit, the transistor is in active mode and $V_{C} = 2 V$. To get $V_{C} = 4 V$, we replace $R_{C}$ with $R′_{C}$. Then the ratio $R'_{C}$/ $R_{C}$ is _________.
In the following circuit, the transistor is in active mode and $V_{C} = 2 V$. To get $V_{C} = 4 V$, we replace $R_{C}$ with $R′_{C}$. Then the ratio $R'_{C}$/ $R_{C}$ i...
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60
GATE Electrical 2015 Set 1 | Question: 14
In the given circuit, the silicon transistor has $\beta = 75$ and a collector voltage $V_{C} = 9V$. Then the ratio of $R_{B}$ and $R_{C}$ is _________.
In the given circuit, the silicon transistor has $\beta = 75$ and a collector voltage $V_{C} = 9V$. Then the ratio of $R_{B}$ and $R_{C}$ is _________.
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61
GATE Electrical 2015 Set 1 | Question: 15
In the $4 \times 1$ multiplexer, the output $F$ is given by $F = A \oplus B$. Find the required input $'I_{3}, I_{2}, I_{1}, I_{0}'$. $1010$ $0110$ $1000$ $1110$
In the $4 \times 1$ multiplexer, the output $F$ is given by $F = A \oplus B$. Find the required input $'I_{3}, I_{2}, I_{1}, I_{0}'$.$1010$$0110$$1000$$1110$
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GATE Electrical 2016 Set 1 | Question: 36
The current state $Q_{A} Q_{B}$ of a two $JK$ flip-flop system is $00$. Assume that the clock rise-time is much smaller than the delay of the $JK$ flip-flop. The next state of the system is $00$ $01$ $11$ $10$
The current state $Q_{A} Q_{B}$ of a two $JK$ flip-flop system is $00$. Assume that the clock rise-time is much smaller than the delay of the $JK$ flip-flop. The next sta...
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