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Most answered questions in Analog and Digital Electronics

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GATE Electrical 2018 | Question: 14
In the logic circuit shown in the figure, $Y$ is given by $Y=ABCD$ $Y=(A+B)(C+D)$ $Y=A+B+C+D$ $Y=AB+CD$
In the logic circuit shown in the figure, $Y$ is given by$Y=ABCD$$Y=(A+B)(C+D)$$Y=A+B+C+D$$Y=AB+CD$
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GATE Electrical 2019 | Question: 35
The output expression for the Karnaugh map shown below is $Q \bar{R} +S$ $Q \bar{R} + \bar{S}$ $QR+S$ $Q R +\bar{S}$
The output expression for the Karnaugh map shown below is$Q \bar{R} +S$$Q \bar{R} + \bar{S}$$QR+S$$Q R +\bar{S}$
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GATE Electrical 2019 | Question: 36
In the circuit shown below, $X$ and $Y$ are digital inputs, and $Z$ is a digital output. The Equivalent circuit is a NAND gate NOR gate XOR gate XNOR gate
In the circuit shown below, $X$ and $Y$ are digital inputs, and $Z$ is a digital output. The Equivalent circuit is aNAND gateNOR gateXOR gateXNOR gate
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GATE Electrical 2017 Set 2 | Question: 10
For a $3$-input logic circuit shown below, the output $Z$ can be expressed as $Q+\overline{R}$ $P\overline{Q}+R$ $\overline{Q}+R$ $P+\overline{Q}+R$
For a $3$-input logic circuit shown below, the output $Z$ can be expressed as $Q+\overline{R}$$P\overline{Q}+R$$\overline{Q}+R$$P+\overline{Q}+R$
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GATE Electrical 2017 Set 1 | Question: 36
The output expression for the Karnaugh map shown below is $B \overline{D}+BCD$ $B \overline{D}+AB$ $\overline{B}D+ABC$ $B \overline{D}+ABC$
The output expression for the Karnaugh map shown below is$B \overline{D}+BCD$$B \overline{D}+AB$$\overline{B}D+ABC$$B \overline{D}+ABC$
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GATE Electrical 2017 Set 1 | Question: 13
The Boolean expression $AB+A\bar{C}+BC$ simplifies to $BC + A\bar{C}$ $AB + A\bar{C} + B$ $AB + A\bar{C}$ $AB + BC$
The Boolean expression $AB+A\bar{C}+BC$ simplifies to$BC + A\bar{C}$$AB + A\bar{C} + B$$AB + A\bar{C}$$AB + BC$
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GATE Electrical 2013 | Question: 39
In the circuit shown below the op-amps are ideal. Then $V_{out}$ in Volts is $4$ $6$ $8$ $10$
In the circuit shown below the op-amps are ideal. Then $V_{out}$ in Volts is$4$$6$$8$$10$
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GATE Electrical 2013 | Question: 18
A band-limited signal with a maximum frequency of $5\:kHz$ is to be sampled. According to the sampling theorem, the sampling frequency in $kHz$ which is not valid is $5$ $12$ $15$ $20$
A band-limited signal with a maximum frequency of $5\:kHz$ is to be sampled. According to the sampling theorem, the sampling frequency in $kHz$ which is not valid is$5$$1...
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GATE Electrical 2013 | Question: 14
The input impedance of the permanent magnet moving coil $(PMMC)$ voltmeter is infinite. Assuming that the diode shown in the figure below is ideal, the reading of the voltmeter in Volts is $4.46$ $3.15$ $2.23$ $0$
The input impedance of the permanent magnet moving coil $(PMMC)$ voltmeter is infinite. Assuming that the diode shown in the figure below is ideal, the reading of the vol...
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29
GATE Electrical 2014 Set 3 | Question: 48
In the bridge circuit shown, the capacitors are loss free. At balance, the value of capacitance $C_1$ in microfarad is _________.
In the bridge circuit shown, the capacitors are loss free. At balance, the value of capacitance $C_1$ in microfarad is _________.
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GATE Electrical 2014 Set 2 | Question: 51
A $JK$ flip flop can be implemented by $T$ flip-flops. Identify the correct implementation.
A $JK$ flip flop can be implemented by $T$ flip-flops. Identify the correct implementation.
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GATE Electrical 2014 Set 2 | Question: 29
Assuming the diodes to be ideal in the figure, for the output to be clipped, the input voltage $v_i$ must be outside the range $-1$ $V$ to $-2$ $V$ $-2$ $V$ to $-4$ $V$ $+1$ $V$ to $-2$ $V$ $+2$ $V$ to $-4$ $V$
Assuming the diodes to be ideal in the figure, for the output to be clipped, the input voltage $v_i$ must be outside the range$-1$ $V$ to $-2$ $V$$-2$ $V$ to $-4$ $V$$+1$...
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39
GATE Electrical 2014 Set 2 | Question: 22
The transistor in the given circuit should always be in active region. Take $V_{CE(sat)}$ = $0.2$ $V$ , $V_{BE}$=$0.7$ $V$. The maximum value of $R_c$ in $Ω$ which can be used, is ______________.
The transistor in the given circuit should always be in active region. Take $V_{CE(sat)}$ = $0.2$ $V$ , $V_{BE}$=$0.7$ $V$. The maximum value of $R_c$ in $Ω$ which can b...
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GATE Electrical 2014 Set 2 | Question: 21
Which of the following is an invalid state in an $8$-$4$-$2$-$1$ Binary Coded Decimal counter $1$ $0$ $0$ $0$ $1$ $0$ $0$ $1$ $0$ $0$ $1$ $1$ $1$ $1$ $0$ $0$
Which of the following is an invalid state in an $8$-$4$-$2$-$1$ Binary Coded Decimal counter$1$ $0$ $0$ $0$$1$ $0$ $0$ $1$$0$ $0$ $1$ $1$$1$ $1$ $0$ $0$
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