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Hot questions in Analog and Digital Electronics
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GATE Electrical 2021 | Question: 37
A counter is constructed with three $D$ flip-flops. The input-output pairs are named $(D_{0},\:Q_{0})$, $(D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$, where the subscript $0$ denotes the least significant bit. The output sequence is desired to be the Gray- ... $\overline{Q_{2}}Q_{0}+Q_{1}\overline{Q_{0}}$ $Q_{2}Q_{1}+\overline{Q_{2}}\:\overline{Q_{1}}$
A counter is constructed with three $D$ flip-flops. The input-output pairs are named $(D_{0},\:Q_{0})$, $(D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$, wher...
Arjun
15.9k
points
Arjun
asked
Feb 19, 2021
Analog and Digital Electronics
gateee-2021
analog-and-digital-electronics
sequential-circuit
flip-flops
+
–
1
votes
1
answer
2
GATE Electrical 2015 Set 2 | Question: 38
A Boolean function $f(A, B, C, D) = \prod (1,5,12,15)$ is to be implemented using an $8 \times 1$ multiplexer ($A$ is $MSB$). The inputs $ABC$ are connected to the select inputs $S_{2} S_{1} S_{0}$ of the multiplexer respectively. Which one of the following ... $D, 1, D, 1, 1, 1, \overline{D}, D$ $\overline{D}, 0, \overline{D}, 0, 0, 0,D, \overline{D}$
A Boolean function $f(A, B, C, D) = \prod (1,5,12,15)$ is to be implemented using an $8 \times 1$ multiplexer ($A$ is $MSB$). The inputs $ABC$ are connected to the selec...
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2015-ee-2
analog-and-digital-electronics
combinational-circuits
multiplexer
+
–
0
votes
0
answers
3
GATE Electrical 2019 | Question: 35
The output expression for the Karnaugh map shown below is $Q \bar{R} +S$ $Q \bar{R} + \bar{S}$ $QR+S$ $Q R +\bar{S}$
The output expression for the Karnaugh map shown below is$Q \bar{R} +S$$Q \bar{R} + \bar{S}$$QR+S$$Q R +\bar{S}$
Arjun
15.9k
points
Arjun
asked
Feb 12, 2019
Analog and Digital Electronics
gate2019-ee
analog-and-digital-electronics
boolean-algebra
k-map
+
–
0
votes
0
answers
4
GATE Electrical 2019 | Question: 36
In the circuit shown below, $X$ and $Y$ are digital inputs, and $Z$ is a digital output. The Equivalent circuit is a NAND gate NOR gate XOR gate XNOR gate
In the circuit shown below, $X$ and $Y$ are digital inputs, and $Z$ is a digital output. The Equivalent circuit is aNAND gateNOR gateXOR gateXNOR gate
Arjun
15.9k
points
Arjun
asked
Feb 12, 2019
Analog and Digital Electronics
gate2019-ee
analog-and-digital-electronics
combinational-circuits
logic-gates
+
–
2
votes
1
answer
5
GATE Electrical 2014 Set 3 | Question: 21
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $X$ is the don’t care condition, and $Q$ is the output representing the state. The logic gate represented by the state diagram is $XOR$ $OR$ $AND$ $NAND$
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $X$ is the don’t care condition, and $Q$ is the output representing t...
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2014-ee-3
analog-and-digital-electronics
combinational-circuits
logic-gates
+
–
0
votes
0
answers
6
GATE Electrical 2012 | Question: 7
In the sum of products function $f(X,Y,Z) = \Sigma(2,3,4,5)$, the prime implicants are $\overline{X}Y, X \overline{Y}$ $\overline{X}Y, X \overline{Y}\overline{Z}, X \overline{Y}Z$ $\overline{X} Y \overline{Z}, \overline{X}YZ, X \overline{Y}$ $\overline{X} Y \overline{Z}, \overline{X}YZ, X \overline{Y} \overline{Z}, X \overline{Y}Z$
In the sum of products function $f(X,Y,Z) = \Sigma(2,3,4,5)$, the prime implicants are$\overline{X}Y, X \overline{Y}$$\overline{X}Y, X \overline{Y}\overline{Z}, X \overli...
Andrijana3306
1.4k
points
Andrijana3306
asked
Mar 23, 2018
Analog and Digital Electronics
gate2012-ee
analog-and-digital-electronics
boolean-algebra
sum-of-products
+
–
0
votes
1
answer
7
GATE Electrical 2018 | Question: 14
In the logic circuit shown in the figure, $Y$ is given by $Y=ABCD$ $Y=(A+B)(C+D)$ $Y=A+B+C+D$ $Y=AB+CD$
In the logic circuit shown in the figure, $Y$ is given by$Y=ABCD$$Y=(A+B)(C+D)$$Y=A+B+C+D$$Y=AB+CD$
Arjun
15.9k
points
Arjun
asked
Feb 19, 2018
Analog and Digital Electronics
gate2018-ee
analog-and-digital-electronics
logic-gates
boolean-algebra
+
–
0
votes
0
answers
8
GATE Electrical 2018 | Question: 37
Digital input signals A, B, C with A as the MSB and C as the LSB are used to realize the Boolean function $F=m_0+m_2+m_3+m_5+m_7$, where $m_i$ denotes the $i$ th minterm. In addition, $F$ has a don't care for $m_1$. The simplified expression for $F$ is given by ... $\overline{A}+C$ $\overline{C}+A$ $\overline{A} C + BC + A \overline{C}$
Digital input signals A, B, C with A as the MSB and C as the LSB are used to realize the Boolean function $F=m_0+m_2+m_3+m_5+m_7$, where $m_i$ denotes the $i$ th minterm...
Arjun
15.9k
points
Arjun
asked
Feb 19, 2018
Analog and Digital Electronics
gate2018-ee
analog-and-digital-electronics
boolean-algebra
+
–
0
votes
0
answers
9
GATE Electrical 2018 | Question: 36
Which one of the following statements is true about the digital circuit shown in the figure It can be used for dividing input frequency by $3$ It can be used for dividing input frequency by $5$ It can be used for dividing input frequency by $7$ It cannot be reliably used as a frequency divider due to disjoint internal cycles
Which one of the following statements is true about the digital circuit shown in the figureIt can be used for dividing input frequency by $3$It can be used for dividing i...
Arjun
15.9k
points
Arjun
asked
Feb 19, 2018
Analog and Digital Electronics
gate2018-ee
analog-and-digital-electronics
sequential-circuit
counters
+
–
0
votes
0
answers
10
GATE Electrical 2017 Set 2 | Question: 49
For the synchronous sequential circuit shown below, the output $Z$ is zero for the initial conditions $Q_{A}, Q_{B}, Q_{C}= Q'_{A}, Q'_{B}, Q'_{C}=100$ The minimum number of clock cycles after which the output $Z$ would again become zero is _________.
For the synchronous sequential circuit shown below, the output $Z$ is zero for the initial conditions $Q_{A}, Q_{B}, Q_{C}= Q'_{A}, Q'_{B}, Q'_{C}=100$The minimum number ...
Arjun
15.9k
points
Arjun
asked
Feb 26, 2017
Analog and Digital Electronics
gate2017-ee-2
numerical-answers
analog-and-digital-electronics
sequential-circuit
counters
+
–
0
votes
0
answers
11
GATE Electrical 2017 Set 1 | Question: 36
The output expression for the Karnaugh map shown below is $B \overline{D}+BCD$ $B \overline{D}+AB$ $\overline{B}D+ABC$ $B \overline{D}+ABC$
The output expression for the Karnaugh map shown below is$B \overline{D}+BCD$$B \overline{D}+AB$$\overline{B}D+ABC$$B \overline{D}+ABC$
Arjun
15.9k
points
Arjun
asked
Feb 26, 2017
Analog and Digital Electronics
gate2017-ee-1
analog-and-digital-electronics
boolean-algebra
k-map
+
–
0
votes
0
answers
12
GATE Electrical 2017 Set 2 | Question: 10
For a $3$-input logic circuit shown below, the output $Z$ can be expressed as $Q+\overline{R}$ $P\overline{Q}+R$ $\overline{Q}+R$ $P+\overline{Q}+R$
For a $3$-input logic circuit shown below, the output $Z$ can be expressed as $Q+\overline{R}$$P\overline{Q}+R$$\overline{Q}+R$$P+\overline{Q}+R$
Arjun
15.9k
points
Arjun
asked
Feb 26, 2017
Analog and Digital Electronics
gate2017-ee-2
analog-and-digital-electronics
combinational-circuits
logic-gates
+
–
0
votes
0
answers
13
GATE Electrical 2017 Set 1 | Question: 13
The Boolean expression $AB+A\bar{C}+BC$ simplifies to $BC + A\bar{C}$ $AB + A\bar{C} + B$ $AB + A\bar{C}$ $AB + BC$
The Boolean expression $AB+A\bar{C}+BC$ simplifies to$BC + A\bar{C}$$AB + A\bar{C} + B$$AB + A\bar{C}$$AB + BC$
Arjun
15.9k
points
Arjun
asked
Feb 26, 2017
Analog and Digital Electronics
gate2017-ee-1
analog-and-digital-electronics
boolean-algebra
+
–
0
votes
0
answers
14
GATE Electrical 2013 | Question: 37
The clock frequency applied to the digital circuit shown in the figure below is $1$ $kHz$. If the initial state of the output $Q$ of the flip-flop is ‘$0$’, then the frequency of the output waveform $Q$ in $kHz$ is $0.25$ $0.5$ $1$ $2$
The clock frequency applied to the digital circuit shown in the figure below is $1$ $kHz$. If the initial state of the output $Q$ of the flip-flop is ‘$0$’, then the ...
piyag476
1.5k
points
piyag476
asked
Feb 11, 2017
Analog and Digital Electronics
gate2013-ee
analog-and-digital-electronics
sequential-circuit
flip-flop
+
–
0
votes
0
answers
15
GATE Electrical 2014 Set 3 | Question: 51
A $3$-$bit$ gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is $0002$. The output is pulled $high$. The output of the circuit follows the sequence $I_0$, $1$, $1$, $I_1$, $I_3$, $1$, $1$, $I_2$ ... $1$, $I_1$, $I_2$, $1$, $I_3$,$1$ $I_0$, $I_1$, $I_2$, $I_3$, $I_0$, $I_1$, $I_2$, $I_3$
A $3$-$bit$ gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is $0002$. The output is pulled $high$....
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2014-ee-3
binary-code
counter
multiplexer
+
–
1
votes
0
answers
16
GATE Electrical 2015 Set 1 | Question: 37
The figure shows a digital circuit constructed using negative edge triggered $J-K$ flip flops. Assume a starting state of $Q_{2}Q_{1}Q_{0}=000$. This state $Q_{2}Q_{1}Q_{0}=000$ will repeat after _______ number of cycles of the clock $CLK$.
The figure shows a digital circuit constructed using negative edge triggered $J-K$ flip flops. Assume a starting state of $Q_{2}Q_{1}Q_{0}=000$. This state $Q_{2}Q_{1}Q_{...
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2015-ee-1
flip-flops
latches
numerical-answers
+
–
0
votes
0
answers
17
GATE Electrical 2013 | Question: 44
Thyristor $T$ in the figure below is initially off and is triggered with a single pulse of width $10$ $μs$. It is given that $L=\bigg(\dfrac{100}{\pi }\bigg)\mu H$ and $C=\bigg(\dfrac{100}{\pi }\bigg)\mu F$. Assuming latching and holding currents of the ... zero and the initial charge on $C$ is zero, $T$ conducts of $10\mu s$ $50\mu s$ $100\mu s$ $200\mu s$
Thyristor $T$ in the figure below is initially off and is triggered with a single pulse of width $10$ $μs$. It is given that $L=\bigg(\dfrac{100}{\pi }\bigg)\mu H$ and...
piyag476
1.5k
points
piyag476
asked
Feb 11, 2017
Analog and Digital Electronics
gate2013-ee
gate-signal
converters
+
–
0
votes
0
answers
18
GATE Electrical 2015 Set 1 | Question: 33
The single-phase full-bridge voltage source inverter (VSI), shown in figure, has an output frequency of $50 \: \text{ Hz}$. It uses unipolar pulse width modulation with switching frequency of $50$ kHz and modulation index of $0.7$. ... the amplitude of the fundamental component in the output voltage $V_{\text{o}}$ (in Volt) under steady-state is ________.
The single-phase full-bridge voltage source inverter (VSI), shown in figure, has an output frequency of $50 \: \text{ Hz}$. It uses unipolar pulse width modulation with s...
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2015-ee-1
modulation-index
pulse-width-modulation
numerical-answers
+
–
0
votes
0
answers
19
GATE Electrical 2015 Set 2 | Question: 8
In the following circuit, the input voltage $V_{in}$ is $100 \sin(100 \pi t)$. For $100 \pi RC = 50$, the average voltage across $R$ (in Volts) under steady-state is nearest to $100$ $31.8$ $200$ $63.6$
In the following circuit, the input voltage $V_{in}$ is $100 \sin(100 \pi t)$. For $100 \pi RC = 50$, the average voltage across $R$ (in Volts) under steady-state is near...
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2015-ee-2
steady-state-operation
diodes
+
–
0
votes
0
answers
20
GATE Electrical 2014 Set 3 | Question: 55
A single-phase voltage source inverter shown in figure is feeding power to a load. The triggering pulses of the devices are also shown in the figure. If the load current is sinusoidal and is zero at $0,\pi , 2\pi$ …, the node voltage $V_{AO}$ has the waveform
A single-phase voltage source inverter shown in figure is feeding power to a load. The triggering pulses of the devices are also shown in the figure.If the load current i...
makhdoom ghaya
9.4k
points
makhdoom ghaya
asked
Feb 11, 2017
Analog and Digital Electronics
gate2014-ee-3
pulses
invertor
+
–
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